Intel Nehalem

  • The integrated memory controller in Nehalem is native to DDR3 memory and each CPU will support three memory channels and three DIMMS per channel. We could be seeing motherboards with nine DIMM slots at the enthusiast end of the market. It will support buffered and un-buffered DIMMs.

  • Intel has just released further details on its successor to the Core 2 CPU, which will be in production towards the end of 2008. It's a yet to be named CPU, however, so for now we will call it by its codename, Nehalem. Nehalem will be built using a 45nm process, so it will be small and scalable. Intel says it will be available in versions from two to eight cores.

  • Most interestingly, Nehalem will feature Simultaneous Multi-Threading (SMT). This will allow each of Nehalem's cores to process two software threads simultaneously (similar to what Hyperthreading did in the Pentium 4). Essentially, a quad-core CPU based on the Nehalem microarchitecture will be able to work on eight threads at once.

  • Each core in Nehalem will have access to three levels of cache; a 64KB level one cache, along with a low-latency 256KB level two cache will be exclusive to each core, but an 8MB level three cache will be shared between all cores (and this size will vary depending on how many cores the CPU has). The level two cache acts as a buffer between the core and the level three cache, so the third level does not see requests for data from all cores simultaneously. This should help eliminate bottlenecks in performance.

  • Nehalem takes the best parts of the Core 2 CPU microarchitecture, such as its ability to process four instructions per clock cycle, and adds even more features and parallelism to create a new microarchitecture. From the slide, you can see some major additions: Nehalem will have an integrated DDR3 memory controller and a three-level cache.

  • Quick Path Interconnect, (aka QPI) is a point-to-point, low latency interconnect that replaces the front side bus. It's used to connect the CPU to the new controller hub (codenamed Tylersburg) and will also be used to connect one CPU to another in a dual-socket design. Initially, each QPI link will supply 25.6GBps of total bandwidth.

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